Improvements in IC technology are leading to continued increases in IC operating speeds. For example, the recently introduced SiGe BiCMOS technology offers a tremendous increase in on-chip signal bandwidth in the areas of analog and mixed signal (AMS) design, providing operating speeds in the region of tens of Gigahertz. As operating speeds reach the multi-Gigahertz range, on-chip interconnect lines, i.e. wires connecting circuit components, can have a major impact on IC performance. High speed design is characterized by a frequent need for true-transient time-domain simulations, high importance of signal integrity, and characteristic bandwidths in the microwave region. Thus a consideration of on-chip interconnect line (“interconnect”) effects becomes necessary. Moreover, early incorporation of interconnects in the design process is highly desirable because a traditional post-layout treatment of on-chip interconnects can lead to numerous design iterations or a significant amount of over-design. To address these issues, our copending U.S. Pat. application Ser. No. 10/091,934, filed 6 Mar. 2002, discloses an interconnect-aware IC design methodology in which interconnects can be modeled as transmission lines (“T-lines”) and incorporated in the design at an early stage of the design process. This system is also discussed in “An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 GHz) On-Chip Transmission Line Approach”, D. Goren et al., IEEE DATE'02 conference, Paris, Mar. 4–8 2002. The system is explained briefly below with reference to FIG. 1 of the accompanying drawings.
The flow chart of FIG. 1 illustrates the basic steps in an exemplary design process embodying the aforementioned methodology. As with conventional IC design processes, the overall process is typically implemented via a CAD (Computer-Aided Design) system under control of a designer who provides the inputs required during the design process, the CAD system incorporating software tools for performing various processing steps and assisting the designer with the various design stages. As will be apparent to those skilled in the art, the basic steps of the FIG. 1 process correspond broadly to those of a conventional IC design flow while differing in key respects explained in the following.
Step 1 of the FIG. 1 flow represents the initial stage of defining a high level design of the IC. This typically includes the usual architecture and floor plan definitions, whereby major design blocks are defined and their locations broadly determined. Thus, the overall design project is defined on a system level in this stage. However, in contrast to conventional design flows, certain interconnects in the high level design are selected in this early design phase for modeling as T-lines. These are the “critical interconnects”, and identification of these interconnects is represented by step 2 of the FIG. 1 flow. Particular criteria for identifying critical interconnects will be discussed below. Suffice to say here that the critical interconnects are usually only a small subset of the totality of interconnects in a given design. Step 2 also involves defining the T-line models to represent the critical interconnects. For each critical interconnect, a T-line structure is defined by selecting a desired structure from a predefined set of structures. A basic feature of these structures is that most of the electric field lines and the current return path are contained within the structure boundary. Examples of T-line structures which can be included in this set are detailed in the above-referenced documents and will be described further below. Briefly, however, these predefined structures represent respective, generic arrangements of signal wires and shielding, with variable geometrical parameters (height, width, separation, etc.) for the various elements of the structure. The required geometrical parameters for the T-line structure selected for a given interconnect are defined in response to input by the designer. A corresponding T-line model is then defined via an embedded algorithm implemented by a T-line modeling component of the system. The T-line models used here are based on RLC (resistance-inductance-capacitance) ladder networks, with the particular network structure and RLC component values being determined by the modeling algorithm.
Once the critical interconnect lines have been identified and their equivalent T-line models defined, these are treated in the same way as other components in the subsequent design process. In particular, in step 3 of the design flow a schematic design of the IC is defined. Here, circuit components such as transistors, resistors, connecting wires, etc. may be defined in the usual way, with the connecting wires generally being defined as ideal wires at this stage. However, the T-line models for critical interconnects are also included in the schematic design, with possible refinement of their underlying geometrical parameters and hence component values. Thus, all on-chip T-lines are automatically net-listed and simulated together with other circuit components, and are treated equally throughout the design process. Further lines may also be identified as critical interconnects at this stage. Thus, the design flow may refer back from step 3 to steps 1 and 2 as indicated by the arrow in the figure, to account for such refinements of the preliminary high level design.
Next, in step 4 of the design process a physical (layout) design is defined based on the schematic design. In this step, the physical location and layout of circuit elements and wires on the IC are defined, along with the various component parameters. The T-line models are passed into the layout design as parameterized cells (p-cells) whereby each model forms an identifiable, unitary component of the design. The p-cells are correct by construction both from the DRC (Design Rule Checking) and LVS (Layout Versus Schematic) points of view. Here, the actual lengths of T-lines may differ slightly from their schematic level values, so that some stretching and bending may be required with consequent adjustment of T-line parameters. Thus, back-annotation from the layout design to the schematic design step may be performed to account for such adjustments.
The next stage of the design flow is the post-layout extraction step 5. Here, a software extraction tool of the design system extracts component parameters from the layout design for simulation purposes in the usual way. Wires modeled as T-lines are recognized here and treated as any other library elements, namely their geometrical parameters are extracted and transferred into the same model equations for post-layout simulation. Wires not modeled as T-lines undergo the standard extraction procedure of conventional systems, whereby an automatic approximate calculation is performed by the extraction tool for wire non-ideal properties. This is faster but less accurate than the special treatment applied to critical interconnects. The complete netlist, combining both the T-line models and the other layout-extracted components, is then simulated in step 6 of the design flow, the simulated results being compared to the original design requirements to complete a bottom-up verification of the design process. If discrepancies are found, the design process may revert to step 4 as indicated in the figure for appropriate modification of the design. However, correct choice of critical interconnects in the earlier design steps makes a one-iteration success highly likely.
As already mentioned, the T-line structures from which the T-line models are derived in the above system are based on the “closed environment concept”, whereby the majority of electric field lines are closed within the structure cross-section and the structure contains its own current return path, i.e. the sum of the currents in its cross-section is zero. This concept is valid for design areas such as AMS design which are characterized by relatively sparse layout (and few crossing lines) in all metal layers. In other design areas such as CMOS design, where design is dense and Manhattan layout is used, the closed environment concept becomes inapplicable where critical interconnects are affected by crossing lines, i.e. lines which cross critical interconnects in a higher or lower layer of the IC structure. For example, where a critical interconnect runs beneath or above a perpendicular line such as a bus, the effect on T-line behavior can be considerable. Consider for example a crossing line in the form of a 64-bit bus consisting of a group of 2 μm wires separated by 1 μm, such that the bus width reaches 190 μm, interference caused by the bus can clearly have a significant effect on T-line behavior. Accordingly, an IC design methodology which can accommodate such crossing line effects would be highly desirable.